In the field of consumer electronic devices, such as wireless phones and portable music players, there is constant pressure to make the devices more compact, less expensive, and more rich with features. In turn, the manufacturers of such devices place the same pressures on each of their suppliers. Traditionally, larger circuit boards could be used to accommodate the additional, oftentimes more powerful, electronic components necessary to provide the desired features. Today, however, the increased pressure to minimize the overall size of electronic devices carries over to the circuit boards that power and control them.
Thus, even as more robust functionality is added to device circuitry, the semiconductor packaging containing the device circuitry must continually decrease in size. Early semiconductor packaging techniques provided a single horizontal layer of silicon chips or die (e.g., integrated circuits (“ICs”), memory chips) to be mounted side-by-side on a substrate and encapsulated or enclosed within a package. Today, packaging technologies have evolved to allow two or more die of varying function or technology (e.g., logic, analog, mixed-signal) to be stacked or integrated on a substrate or printed circuit board (“PCB”) in a vertical fashion. This concept, often referred to as “die stacking” or manufacturing a “system-in-package” (“SiP”), significantly increases the amount of silicon chip area that can be housed within a single package of a given footprint, conserving precious real estate on the PCB and simplifying the board assembly process.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.